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Ordering number : EN*3587B
CMOS LSI
LC7573N, 7573NM
1/2 Duty VFD Driver for Frequency Display
Preliminary Overview
The LC7573N and LC7573NM are 1/2 duty VFD drivers that can be used for electronic tuning frequency display and other applications under the control of a controller. These products can directly drive VFDs with up to 38 segments.
Package Dimensions
unit: mm 3061-DIP30S
[LC7573N]
Features
* 38 segment outputs * Noise reduction circuits are built into the output drivers. * Serial data input supports CCB* format communications with the system controller. * Switching between digital and analog dimmers under serial data control * High generality since display data is displayed without the intervention of a decoder * All segments can be turned off with the BLK pin
SANYO: DIP30S * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
unit: mm 3073A-MFP30S
[LC7573NM]
Pin Assignment
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O2095HA (OT)/3242JN No.3587-1/10
LC7573N, 7573NM
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VFL max VIN1 VIN2 VOUT1 VOUT2 IOUT1 IOUT2 Pd max Topr Tstg VDD VFL DI, CL, CE, BLK, DIM OSC S1 to S19, G1, G2 OSC S1 to S19 G1, G2 Ta = 85C Conditions Ratings -0.3 to +6.5 -0.3 to +21.0 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to VFL + 0.3 -0.3 to VDD + 0.3 5 30 150 -40 to +85 -50 to +125 Unit V V V V V V mA mA mW C C
Input voltage
Output voltage
Output current Allowable power dissipation Operating temperature Storage temperature
Allowable Operating Ranges at Ta = -40 to +85C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Supply voltage Input high level voltage Input low level voltage Guaranteed oscillator range Recommended external resistance Recommended external capacitance Low level clock pulse width High level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time BLK switching time Input voltage range Symbol VDD VFL VIH VIL fOSC ROSC COSC toL toH tds tdh tcp tcs tch tc VIN VDD VFL DI, CL, CE, BLK DI, CL, CE, BLK OSC OSC OSC CL: Figure 1 CL: Figure 1 DI, CL: Figure 1 DI, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 BLK, CE: Figure 3 DIM 0.5 0.5 0.5 0.5 0.5 0.5 0.5 10 0 +5.5 Conditions min 4.5 8 0.8 VDD 0 0.4 1.6 12 50 typ 5.0 12 max 5.5 18 5.5 0.2 VDD 3.0 Unit V V V V MHz k pF s s s s s s s s V
Electrical Characteristics in the Allowable Operating Ranges
Parameter Input high level current Input low level current Output high level voltage Output low level voltage Oscillator frequency Hysteresis voltage A/D converter linearity error Current drain Symbol IIH IIL VOH1 VOH2 VOL fOSC VH Err IDD Conditions DI, CL, CE, BLK, DIM: VI = 5.5 V DI, CL, CE, BLK, DIM: VI = 0 V S1 to S19: IO = 2 mA G1, G2: IO = 25 mA S1 to S19, G1, G2: IO = -5 A, Ta = 25C ROSC = 12 k, COSC = 50 pF DI, CL, CE, BLK DIM Outputs open: fOSC = 1.6 MHz 0.5 -1/2 +1/2 5 -5 VFL - 0.6 VFL - 0.6 0.125 0.25 1.6 0.5 min typ max 5 Unit A A V V V MHz V LSB mA
No. 3587-2/10
LC7573N, 7573NM 1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 1 Block Diagram
No. 3587-3/10
LC7573N, 7573NM Pin Functions
Pin No. 1 2 5 3 Pin VFL VDD VSS OSC I/O -- -- -- I/O Function Driver block power supply. A voltage of between 8.0 and 18.0 V must be supplied. Logic block power supply. A voltage of between 4.5 and 5.5 V must be supplied. Ground. Must be connected to the system ground. Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. Display off control input BLK = low (VSS): Display off (G1 and G2 = low) BLK = high (VDD): Display on Note that serial data can be transferred while the display is turned off. Serial data transfer inputs. These pins must be connected to the system controller. CL: synchronization clock DI: transfer data CE: chip enable Handling when unused -- -- -- VDD
4
BLK
I
GND
7 8 9
CL DI CE I
GND
6
DIM
I
When the analog dimmer is selected, the analog voltage applied to this pin controls the duty of the G1 and G2 digit output pins. Since a 6-bit A/D converter is applied to this analog voltage and that result is input to a decoder that provides a built-in dimmer curve, the relationship between the analog voltage and the duty can be specified as a mask program. Note that 63/96 * VDD is the full-scale level for the 6-bit A/D converter. Digit outputs. The frame frequency fO is (fOSC/4096) Hz Segment outputs for displaying the display data transferred by serial data input.
GND
30, 29 28 to 10
G1, G2 S1 to S19
O O
Open Open
Serial Data Transfer Format 1. When CL is stopped at the low level
2. When CL is stopped at the high level
Figure 2
No. 3587-4/10
LC7573N, 7573NM CCB address: Transfer 0010B, as shown in Figure 2. M0: Digital/analog dimmer selection data M0 = 0 ....................................Digital dimmer M0 = 1 ....................................Analog dimmer DM0 to DM9: Dimmer data This data controls the duty of the G1 and G2 digit output pins when the digital dimmer is selected. This data consists of 10 bits, of which DM0 is the LSB. Note that display intensity can be adjusted by controlling the duty of the G1 and G2 digit output pins. (The DM0 to DM9 dimmer data is ignored when the analog dimmer is selected.) SD1 to SD38: Display data SD1 to SD19...........................Display data for the G1 digit output pin SD20 to SD38.........................Display data for the G2 digit output pin SDn (n = 1 to 38) = 1..............Display on SDn (n = 1 to 38) = 0..............Display off T0: Test data The T0 bit must be set to 0. Serial Data Format
Correspondence between Display Data (SD1 to SD38) and Segment Output Pins
Segment output pin S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 G1 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SD16 SD17 SD18 SD19 G2 SD20 SD21 SD22 SD23 SD24 SD25 SD26 SD27 SD28 SD29 SD30 SD31 SD32 SD33 SD34 SD35 SD36 SD37 SD38
No. 3587-5/10
LC7573N, 7573NM Example: Segment output pin S11 is controlled as follows:
Display data SD11 0 0 1 1 SD30 0 1 0 1 Segment output pin S11 state The segments corresponding to both the G1 and G2 digit output pins are off. The segment corresponding to the G2 digit output pin is on. The segment corresponding to the G1 digit output pin is on. The segments corresponding to both the G1 and G2 digit output pins are on.
BLK and the Display Control Since the LSI internal data (SD1 to SD38 and the control data) is undefined when power is first applied, the display is off (G1 and G2 = low) by setting the BLK pin low at the same time as power is applied. Then, meaningless display at power on can be prevented by transferring all 56 bits of serial data from the controller while the display is off and setting BLK pin high after the transfer completes. (See Figure 3.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 3.) * Power on: Logic block power supply (VDD) on Driver block power supply (VFL) on * Power off: Driver block power supply (VFL) off Logic block power supply (VDD) off
Figure 3
No. 3587-6/10
LC7573N, 7573NM Output Waveforms (S1 to S19)
No. 3587-7/10
LC7573N, 7573NM Relation between Segment and Digit Outputs
Figure 4 Descriptions 1. Consider the examples shown in Figure 4, where data is set up so that the segment outputs S1 to S19 output a low level on the G1 digit output timing and a high level on the G2 digit output timing. (Here, the G2 side being lighted) 2. The digit output G1 and G2 waveforms in Example 1 are output when the 10 bits of dimmer data (DM0 to DM9) are set to 3FEH. The relation between t1 and the oscillator frequency fOSC is: t1 = 2/fOSC. For example, if fOSC = 1.6 [MHz], then t1 = 2/1.6 [MHz] = 1.25 [s]. Note that t1 and t2 are the same period in Example 1. 3. The digit output G1 and G2 waveforms in Example 2 are those when the dimmer data (DM0 to DM9) are set to a smaller value. Although the time t1, which is from the point where digit output falls to segment output changes, does not change, the time t2, which is from the point where segment output changes to the time the digit output rises, becomes longer. When the dimmer data (DM0 to DM9) are set to 0FFH and fOSC is 1.6 [MHz], then the frame frequency fO is: fO = 1/(t3 x 2) = fOSC/4096 = 391 [Hz], and, t3 = 1.28 [ms]. Therefore, t2 = (1.28 [ms] - 1.25 [s] x 2) x (3FFH - 0FFH) = 0.96 [ms]. 1023
4. When the dimmer data (DM0 to DM9) are set to an even smaller value, the time t2, which is from the point where segment output changes to the time the digit output rises, becomes even longer, as in Example 3. Note that t1 does not change here, either.
No. 3587-8/10
LC7573N, 7573NM Sample Application Circuit
Usage Notes 1. Notes on the segment and digit waveforms
Figure 5
No. 3587-9/10
LC7573N, 7573NM The segment waveform is distorted by the VFD panel used and the wiring, and furthermore, in the case of being used with essentially no dimming as in the digit waveform 1, as shown in Figure 5, the VFD panel glow dimly. By carefully considering the segment waveform, it can be seen that this problem can be resolved by applying an adequate amount of dimming, as shown in Digit waveform 2. When fOSC is 1.6 [MHz], we recommend using 10 bits of dimmer data in the range 000H to 3E0H.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1995. Specifications and information herein are subject to change without notice. PS No. 3587-10/10

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